1. Technical Field
The present invention relates to a semiconductor device, and more particularly, to a down-converting voltage generating circuit.
2. Related Art
A semiconductor device has a circuit for generating various is internal voltages (VPP, VBB, VCORE, etc.) from an external voltage so as to perform a stable operation. In this case, the internal voltages are generated using a charge-pumping method or down-converting method. The charge-pumping method is used to generate a pumping voltage (VPP), bulk voltage (VBB) or the like, and the down-converting method is used to generate a core voltage (VCORE) that is an internal voltage having a level lower than that of the external voltage, or the like.
FIG. 1 is a circuit diagram of a related art for a down-converting voltage generating circuit.
A voltage generated using the down-converting method is defined as a down-converted voltage VDC, and a circuit for generating the down-converted voltage VDC is defined as a down-converting voltage generating circuit. The related art for a down-converting voltage generating circuit uses a method in which an external voltage is applied as a down-converted voltage VDC in the initial stage of a power-up operation for the purpose of fast ramping of the down converted voltage VDC.
The down-converting voltage generating circuit includes a reference voltage providing unit 10, an initial setting unit 20, and a voltage driving unit 30.
The reference voltage providing unit 10 stably supplies a reference voltage VREF to a first node NODE1 by feeding back an output thereof.
If an activated initial setting signal EXT_ON is applied to the initial setting unit 20, the initial setting unit 20 drops a voltage level of the first node NODE1 to the level of a ground voltage (VSS). The activated signal may be asserted to a logic high level in positive logic or asserted to a logic low level in negative logic. Similarly, a deactivated signal may be deasserted to a logic low level in positive logic or deasserted to a logic high level in negative logic. The initial setting signal EXT_ON is activated in the initial stage of the power-up operation, and is deactivated after a predetermined time elapses.
The voltage driving unit 30 drives and outputs a down-converted voltage VDC from an external voltage VCCE in response to the voltage level of the first node NODE1.
In the related art down-converting voltage generating circuit, if the activated initial setting signal EXT_ON is applied to the initial setting unit 20 in the initial stage of the power-up operation, a first switch N1 is turned on so as to apply the level of the ground voltage VSS to the first node NODE1. Therefore, first to fourth drivers P1 to P4 are turned on so that the external voltage VCCE is outputted as the down-converted voltage VDC.
Subsequently, if the initial setting signal EXT_ON is deactivated, the reference voltage VREF is applied to the voltage driving unit 30, and therefore, the level the down-converted voltage VDC is converged to the level of a target voltage VTG after a predetermined time elapses.
FIG. 2 is a graph illustrating an operation of the related art for the down-converting voltage generating circuit.
The external voltage VCCE rises up to point A and then stabilizes. Since the activated initial setting signal EXT_ON is applied in the initial stage of the power-up operation, the down-converted voltage VDC rises with the external voltage VCCE up to point A, and maintains the voltage of the external voltage VCCE up to point B. In this case, during the period from point A to point B, the down-converted voltage VDC is driven to be as high as the external voltage VCCE, where the voltage VCCE is higher than that of the set target voltage VTG. This may stress any circuitry or device which is expecting a voltage not much greater than VTG.
Subsequently, if the initial setting signal EXT_ON is deactivated at point B, there occurs a period from point B to point C in which the voltage level of the first node NODE1 rises from the level of the ground voltage to the level of the reference voltage VREF. Therefore, the down-converted voltage VDC decreases from the voltage VCCE to the target voltage VTG. However, during the period from before point A, when the down-converted voltage VDC first goes past the target voltage VTG to point C when the down-converted voltage drops down to the target voltage VTG, a circuit receiving the down-converted voltage VTG may malfunction due to an incorrect level of the down-converted voltage VDC.